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ST7LCRE4U1 ST7LCRDIE6
Full-speed USB MCU with smartcard interface
Features
Clock, reset and supply management - Low voltage reset - Halt power saving mode - PLL for generating 48 MHz USB clock using a 4 MHz crystal USB (Universal Serial Bus) host interface - USB 2.0 compliant - CCID v1.0 - Full speed, hubless - Bus-powered, low consumption ISO7816-3 UART Interface - 4 MHz clock generation - Synchronous/asynchronous protocols (T=0, T=1) - Automatic retry on parity error - Programmable baud rate from 372 to 11.625 clock pulses (D=32/F=372) - Card insertion/removal detection Smartcard power supply - Fixed card VCC: 1.8 V, and 3 V - Internal step-up converter for 5 V supplied smartcards (with current of up to 55 mA) using only two external components Device summary
DIE
VFQFPN24(Y1)
- Programmable smartcard internal voltage regulator (1.8 to 3.0V) with current overload protection and 4 kV ESD protection (human body model) for all smartcard Interface I/Os
Development tools - Full hardware/software development package. - Fully compatible with Flash ST7FSCR family for development purposes ECOPACK(R) package
Description
ST7LCRE4U1 and ST7LCRDIE6 are an 8-bit microcontrollers dedicated to smartcard reading applications. They have been developed to be the core of smartcard readers communicating through USB link. Optimized for mass-market applications, it offers a single integrated circuit solution with very few external components.
Part numbers
Table 1.
Features ST7LCRE4U1 Program memory User RAM + USB data buffer Peripherals Operating Supply Package CPU Frequency Operating temperature VFQFPN24 16 Kbyte of ROM 512 + 256 bytes USB full-speed (7 Ep), TBU, watchdog timer, ISO7816-3 interface 4.0 to 5.5 V Die format (Refer to Die Specifications) 4 or 8 MHz 0C to +70 C ST7LCRDIE6
October 2007
Rev 1
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www.st.com 1
ST7LCR
Contents
1 2 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ST7LCR implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 3.2 Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Smartcard interface features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 4.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2.1 4.2.2 4.2.3 4.2.4 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Current injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 4.4
Supply and reset characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4.1 4.4.2 4.4.3 General timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Crystal resonator oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.5 4.6 4.7
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Smartcard supply supervisor electrical characteristics . . . . . . . . . . . . . . 17 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.7.1 4.7.2 4.7.3 Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . . 19 Electromagnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 20
4.8
Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 21
5
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6 7
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Device configuration and ordering information . . . . . . . . . . . . . . . . . . 26 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ST7LCR
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Current injection on I/O port and control pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 I/O port pins characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Low voltage detector and supervisor (LVDs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 General timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Crystal resonator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Typical crystal resonator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Recommended values for 4 MHz crystal resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 RAM and hardware registers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Smartcard supply supervisor electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 USB full-speed electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 24-lead very thin fine pitch quad flat no-lead 5x5mm,0.65mm pitch, mechanical data. . . . 24 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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ST7LCR
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. ST7LCR block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 24-lead VFQFPN package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Smartcard interface reference application - VFQFPN24 pin block diagram . . . . . . . . . . . . . 9 Typical application with an external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Typical application with a crystal resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 USB data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 24-lead very thin fine pitch quad flat no-lead 5x5 mm 0.65 mm pitch, package outline . . . 24 Recommended reflow oven profile (MID JEDEC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 ST7LCR option list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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ST7LCR
1
Description
The ST7LCRE4U1 and ST7LCRDIE6 devices are members of the ST7 microcontroller family designed for USB applications. All devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set. ST7LCRE4U1 and ST7LCRDIE6 are factory-programmed ROM devices. They operate at a 4 MHz external oscillator frequency. Under software control, all devices can be placed in Halt mode, to reduce power consumption when the application is in idle or standby state. The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. The devices include an ST7 Core, up to 16 Kbytes of program memory, up to 512 bytes of user RAM and the following on-chip peripherals:
USB full speed interface with 7 endpoints, programmable in/out configuration and embedded 3.3 V voltage regulator and transceivers (no external components are needed) ISO7816-3 UART interface with programmable baud rate from 372 clock pulses up to 11.625 clock pulses Smartcard supply block able to provide programmable supply voltage and I/O voltage levels to the smartcards Low voltage reset ensuring proper power-on or power-off of the device (selectable by option) 8-bit Timer (TBU)

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ST7LCR Figure 1. ST7LCR block diagram
4 MHz
OSCILLATOR PLL 48 MHz DIVIDER USB DATA BUFFER (256 bytes) USBDP USBDM USBVCC 8 MHz or 4 MHz
ADDRESS AND DATA BUS
OSCIN OSCOUT
USB
ISO7816 UART SUPPLY MANAGER
8-bit TIMER
8-bit CORE ALU LVD RAM (512 bytes) PROGRAM MEMORY (16 Kbytes)
DC/DC CONVERTER
CRDVCC CRDDET CRDIO C4 C8
3/1.8 V Vreg
CRDRST CRDCLK
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ST7LCR
2
Pin description
Figure 2. 24-lead VFQFPN package pinout
GNDA
24
23
22
21
20
19 18
CRDVCC CRDRST CRDCLK C4 CRDIO C8
1
VDDA
GND
VDD
NC
NC
USBVCC DP DM NC NC GND
2
17
3
16
4
15
5
14
6 7 8 9 10 11 12
13
NC
NC
NC
CRDDET
OSCIN
Table 2.
Pin number
Pin description
Level Type Output Input Pin name VCARD supplied Port/control Input Output Main function (after reset) wpu OD PP int Alternate function
VFQFPN24 1 2 3 4 5 6 7 8 9 10 CDRVCC CRDRST CRDCLK C4 CRDIO C8 CRDDET NC NC NC O O O O I/O O I
CT CT CT CT CT CT CT
X X X X X X X X X X X X X
OSCOUT Smartcard supply pin Smartcard reset Smartcard clock Smartcard C4 Smartcard I/O Smartcard C8 Smartcard detection Not used(1) Not used(1) Not used(1)
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ST7LCR Table 2.
Pin number Pin name VFQFPN24 11 12 13 14 15 16 17 18 19 20 21 22 23 24 OSCIN OSCOUT GND NC NC DM DP USBVCC VDDA VDD NC NC GNDA GND S Ground S
1. Pins 8,9,10, and 14 must be connected to ground.
Pin description (continued)
Level Type Output Input VCARD supplied Port/control Input Output Main function (after reset) wpu OD PP int Alternate function
CT CT S
Input/Output oscillator pins. These pins connect a 4 MHz parallel-resonant crystal, or an external source to the on-chip oscillator. Must be held low in normal operating mode. Not used(1) Not used
I/O I/O O S S
CT CT CT
USB Data Minus line USB Data Plus line 3.3 V Output for USB Power supply voltage 4-5.5 V Power supply voltage 4-5.5 V Not used Not used
Legend/abbreviations

Type: I = input, O = output, S = supply In/Output level: CT = CMOS 0.3VDD/0.7VDD with input trigger Output level: HS = 10 mA high sink (on N-buffer only) Port and control configuration: - - Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog Output: OD = open drain, PP = push-pull
8/29
ST7LCR Figure 3. Smartcard interface reference application - VFQFPN24 pin block diagram
VDD C2
24 1
23
22
21
20
19 18 17 16 15 14 13 12
C4
2 3 4
R
D+ D-
C5 C6
5 6 7 8 9 10 11
CL1
CL2
1. Mandatory values for the external components: C1 = 4.7 F, C2 = 100 nF. C1 and C2 must be located close to the chip. C3 = 1 nF C4 = 4.7 F, ESR = 0.5 C5 = 470 pF C6 =100 pF R = 1.5 k L1 = 10 H, 2 Crystal 4.0 MHz, maximum impedance = 100 Cl1, Cl2 (refer Section 4.4.3: Crystal resonator oscillators). D1: BAT42 Shottky
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ST7LCR
3
ST7LCR implementation
ST7LCRE4U1 and ST7LCRDIE6 offer single IC solutions and simplifies the integration of smartcard interfaces into smartcard readers.
3.1
Functionality
A dedicated analog block provides the power supplies 1.8 V and 3 V necessary to interface with different smartcard voltages available on the market. Voltages are selected by software. A dedicated UART interface provides an IS07816 communication port for connection with the smartcard connector. A full-speed USB interface port allows external connection to a host computer.
3.2
Smartcard interface features
The ST7LCRE4U1 and ST7LCRDIE6 include the following features:

Compatibility with asynchronous cards Compatibility with T=0 and T=1 protocols Compatibility with EMV and PC/SC modes. Compliance with ISO 7816-3 and 4 and ability to supply the cards with 1.8 V or 3 V (class A, B or C cards, respectively) Resume/wake-up mode upon smartcard insertion/removal
The reader is able to communicate with smartcards up to the maximum baud rate allowed, namely 344 086 bps (TA1=16) for a clock frequency of 4 MHz. Because the size of the smartcard buffer is 261 bytes, care must be taken not to exceed this size during APDU exchanges when the protocol in use is T=1.
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ST7LCR
4
4.1
Electrical characteristics
Absolute maximum ratings
This product contains devices for protecting the inputs against damage due to high static voltages, however it is advisable to take normal precautions to avoid applying any voltage higher than the specified maximum rated voltages. For proper operation it is recommended that VI and VO be higher than VSS and lower than VDD. Reliability is enhanced if unused inputs are connected to an appropriate logic voltage level (VDD or VSS).
Power considerations
The average chip-junction temperature, TJ, in Celsius can be obtained from:
T J = T A + PD x RthJA
where: TA = Ambient temperature RthJA = Package thermal resistance (junction-to ambient) PD = PINT + PPORT PINT = IDD x VDD (chip internal power) PPORT = Port power dissipation determined by the user Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions is not implied. Exposure to maximum rating for extended periods may affect device reliability. Table 3. Absolute maximum ratings
Ratings Supply voltage Input voltage Output voltage ESD susceptibility ESD susceptibility for card pads Total current into VDD_I (source) Total current out of VSS_I (sink) Value 6.0 VSS - 0.3 to VDD + 0.3 VSS - 0.3 to VDD + 0.3 2000 4000 250 mA 250 Unit V V V V V
Symbol VDD - VSS VIN VOUT ESD ESDCard IVDD_I IVSS_I
Warning:
Direct connection to VDD or VSS of the I/O pins could damage the device in case of program counter corruption (due to unwanted change of the I/O configuration). To guarantee safe conditions, this connection has to be done through a typical 10k pull-up or pull-down resistor.
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ST7LCR Table 4. Thermal characteristics
Ratings Package thermal resistance VFQFPN24 Max. junction temperature Storage temperature range Power dissipation VFQFPN24 Value 42 150 -65 to +150 600 Unit C/W C C mW
Symbol RthJA TJmax TSTG PDmax
4.2
Recommended operating conditions
Operating conditions are given for TA = 0 to +70 C unless otherwise specified.
4.2.1
General operating conditions
Table 5.
Symbol VDD fOSC TA
General operating conditions
Parameter Supply voltage External clock source Ambient temperature range 0 Conditions Min 4.0 Typ Max 5.5 16 70 Unit V MHz C
4.2.2
Current injection
Positive injection
The positive injection current, IINJ+, is applied through protection diodes insulated from the substrate of the die.
Negative injection
The negative injection current, IINJ-, is applied through protection diodes NOT INSULATED from the substrate of the die. The drawback is a small leakage of few A induced inside the die when a negative injection is performed. This leakage is tolerated by the digital structure. The effect depends on the pin which is submitted to the injection. Of course, external digital signals applied to the component must have a maximum impedance close to 50 k. Pure digital pins can tolerate a negative current injection of 1.6 mA. In addition, the best choice is to inject the current as far as possible from the analog input pins. Note: When several inputs are submitted to a current injection, the maximum injection current is the sum of the positive (respectively negative) currents (instantaneous values). Refer to Table 6 for the values of IINJ- and IINJ+.
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ST7LCR
Table 6. Symbol Current injection on I/O port and control pins Parameter Total positive injected current(1) Total negative injected current Conditions VEXTERNAL > VDD (standard I/Os) VEXTERNAL > VCRDVCC (smartcard I/Os) Digital pins VEXTERNAL < VSS Analog pins Min Typ Max 20 20 20 20 Unit mA mA mA mA
IINJ+
IINJ-
1. For SmartCard I/Os, VCRDVCC has to be considered.
4.2.3
Current consumption
Table 7 are measured at TA=0 to +70C, and VDD-VSS=5.5 V unless otherwise specified. Table 7.
Symbol
Current consumption(1)
Parameter Supply current in Run mode(2) Supply current in suspend mode Conditions fOSC = 4 MHz External ILOAD = 0 mA (USB transceiver enabled) External ILOAD = 0 mA (USB transceiver disabled) 50 Min Typ 10 Max 15 500 A 100 Unit mA
IDD
Supply current in Halt mode
1. All I/O pins are in input mode with a static value at VDD or VSS. Clock input (OSCIN) is driven by external square wave. 2. CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS; clock input (OSCIN) driven by external square wave.
4.2.4
I/O port pin characteristics
Table 8 characteristics are measured at TA=0 to +70C. Voltages are referred to VSS unless otherwise specified. Table 8.
Symbol VIL VIH VHYS VOL VOH IL RPU
I/O port pins characteristics
Parameter Input low level voltage Input high level voltage Schmidt trigger voltage hysteresis(1) Output low level voltage for Standard I/O port pins Output high level voltage Input leakage current Pull-up equivalent resistor I=-5mA I=-2mA I=3mA VSS13/29
ST7LCR Table 8.
Symbol tOHL tOHL tOLH tOLH tITEXT
I/O port pins characteristics (continued)
Parameter Output high to low level fall time for high sink I/O port pins (Port D)(2) Output high to low level fall time for standard I/O port pins (Port A, B or C)(2) Output L-H rise time (Port D)(2) Output L-H rise time for standard I/O port pins (Port A, B or C)(2) External interrupt pulse time Conditions Min 6 18 Cl=50 pF 7 19 1 9 14 28 tCPU Typ 8 Max 13 23 ns Unit
1. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested. 2. Guaranteed by design, not tested in production.
4.3
Supply and reset characteristics
Table 9 characteristics are measured for TA = 0 to +70 C, and VDD - VSS = 5.5 V unless otherwise specified. Table 9.
Symbol VIT+ VITVhys VtPOR
Low voltage detector and supervisor (LVDs)
Parameter Reset release threshold (VDD rising) Reset generation threshold (VDD falling) Hysteresis VIT+ - VIT-(1) VDD rise time rate(1) 20 3.3 Conditions Min Typ 3.7 3.5 200 Max 3.9 Unit V V mV ms/V
1. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4.4
4.4.1
Clock and timing characteristics
General timings
Table 10 are measured at TA=0 to +70 C unless otherwise specified. Table 10.
Symbol tc(INST)
General timings
Parameter Instruction cycle time fCPU=4 MHz Interrupt reaction time tv(IT) = tc(INST) + 10 (2) 500 10 fCPU=4 MHz 2.5 750 3000 22 5.5 Conditions Min 2 Typ(1) 3 Max 12 Unit tCPU ns tCPU s
tv(IT)
1. Data based on typical application software. 2. Time measured between interrupt event and interrupt vector fetch. tc(INST) is the number of tCPU cycles needed to finish the current instruction execution.
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ST7LCR
4.4.2
External clock source
Table 11.
Symbol VOSCINH VOSCINL tw(OSCINH) tw(OSCINL) tr(OSCIN) tf(OSCIN) IL
External clock source characteristics
Parameter OSCIN input pin high level voltage OSCIN input pin low level voltage OSCIN high or low time(1) OSCIN rise or fall time OSCx Input leakage current VSSVINVDD see Figure 4 Conditions Min 0.7VDD VSS 15 ns 15 1 A Typ Max VDD 0.3VDD Unit V
1. Data based on design simulation and/or technology characteristics, not tested in production.
Figure 4.
VOSCINH
Typical application with an external clock source
90% 10%
VOSCINL tr(OSCIN) tf(OSCIN) tw(OSCINH) tw(OSCINL)
OSCOUT
fOSC EXTERNAL CLOCK SOURCE OSCIN IL ST7XXX
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ST7LCR
4.4.3
Crystal resonator oscillators
The ST7 internal clock is supplied with one Crystal resonator oscillator. All the information given in this paragraph are based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. Refer to the crystal resonator manufacturer for more details (frequency, package, accuracy...).
Table 12.
Symbol fOSC RF CL1 CL2
Crystal resonator characteristics
Parameter Oscillator Frequency(1) Feedback resistor Recommended load capacitances versus equivalent serial resistance of the crystal resonator (RS) OSCOUT driving current Conditions MP: Medium power oscillator 90 Min Typ 4 150 Max Unit MHz k
See Table 14
(MP oscillator)
22
56
pF
i2
VDD=5V VIN=VSS
(MP oscillator)
1.5
3.5
mA
1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value. Contact crystal resonator manufacturer for more details.
Table 13.
Oscillator Crystal
Typical crystal resonator characteristics
Reference SS3-400-3030/30 Freq. Characteristic(1) fOSC=[30ppm25C,30ppmTa] (Typ) RS=60 CL1 CL2 tSU(osc) (pF) (pF) (ms)(2) 33 33 7~10
MP JAUCH
4 MHz
1. Resonator characteristics given by the crystal resonator manufacturer. 2. tSU(OSC) is the typical oscillator start-up time measured between VDD = 2.8 V and the fetch of the first instruction (with a quick VDD ramp-up from 0 to 5 V (<50 s).
Table 14.
Recommended values for 4 MHz crystal resonator
Min 20 56 pF 56 pF Typ 25 47 pF 47 pF Max 70 22 pF 22 pF
Symbol RSMAX(1) COSCIN COSCOUT
1. RSMAX is the equivalent serial resistor of the crystal (see crystal specification).
16/29
ST7LCR Figure 5. Typical application with a crystal resonator
i2
fOSC OSCIN
WHEN RESONATOR WITH INTEGRATED CAPACITORS
CL1
RESONATOR CL2 OSCOUT
RF ST7XXX
4.5
Memory characteristics
Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. Table 15.
Symbol VRM
RAM and hardware registers characteristics
Parameter Data retention mode(1) Conditions Halt mode (or Reset) Min 2 Typ Max Unit V
1. Minimum VDD supply voltage without losing data stored in RAM (in Halt mode or under Reset) or in hardware registers (only in Halt mode). Not tested in production.
4.6
Smartcard supply supervisor electrical characteristics
Table 16 characteristics are measured for TA = 0 to +70 C, and 4.0 < VDD - VSS < 5.5 V unless otherwise specified.
Table 16.
Symbol
Smartcard supply supervisor electrical characteristics
Parameter Conditions Min Typ Max Unit
3 V regulator output (for IEC7816-3 class B cards) VCRDVCC ISC IOVDET tIDET tOFF tON SmartCard Power Supply Voltage SmartCard Supply Current Current Overload Detection Detection time on Current Overload VCRDVCC Turn off Time VCRDVCC Turn on Time CLOADmax4.7uF CLOADmax 4.7uF 150 170(1) 2.7 3.0 3.3 50 100(1) 1400(1) 750 500 V mA mA s s s
1.8 V regulator output (for IEC7816-3 Class C Cards) VCRDVCC ISC IOVDET SmartCard Power Supply Voltage SmartCard Supply Current Current Overload Detection 1.65 1.8 1.95 20 100(1) V mA mA
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ST7LCR Table 16.
Symbol tIDET tOFF tON
Smartcard supply supervisor electrical characteristics (continued)
Parameter Detection time on Current Overload VCRDVCC Turn off Time VCRDVCC Turn on Time CLOADmax 4.7uF CLOADmax 4.7uF 150 Conditions Min 170(1) Typ Max 1400(1) 750 500 Unit s s s
Smartcard CLKPin VOL VOH TOHL TOLH FVAR FDUTY POL POH ISGND Output Low Level Voltage Output High Level Voltage Output H-L Fall Time(1) Output L-H Rise Time(1) Frequency Duty Signal low variation(1) I=-50uA I=50uA Cl=30pF Cl=30pF VCRDVCC0.5(1) 45 -0.25 VCRDVCC-0.5 15 0.4(1) 20 20 1 55 0.4 VCRDVCC+0.2 5 V V ns ns % % V V mA
cycle(1)
perturbation(1)
Signal high perturbation(1) Short-circuit to Ground(1)
Smartcard I/O Pin VIL VIH VOL VOH IL IRPU TOHL TOLH ISGND Input Low Level Voltage Input High Level Voltage Output Low Level Voltage Output High Level Voltage Input Leakage Current
(1)
0.6VCRDVCC(1) I=-0.5mA I=20uA VSS24
0.5(1) 0.4 (1) VCRDVCC 10 30 0.8 0.8
(1)
V V V V A k s s mA
Pull-up Equivalent Resistance Output H-L Fall Time(1) Output L-H Rise Time Short-circuit to
(1)
Ground(1)
15
Smartcard RST C4 and C8 Pin VOL VOH TOHL TOLH ISGND Output Low Level Voltage Output High Level Voltage Output H-L Fall Time(1) Output L-H Rise Short-circuit to Time(1) I=-0.5mA I=20uA Cl=30pF Cl=30pF VCRDVCC0.5(1) 15 0.4(1) VCRDVCC(1) 0.8 0.8 V V s s mA
Ground(1)
1. Data based on characterization results, not tested in production.
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ST7LCR
4.7
EMC characteristics
Susceptibility tests are performed on a sample basis during product characterization.
4.7.1
Functional EMS (electromagnetic susceptibility)
Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).
ESD: electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard. FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.
Software recommendations The software flowchart must include the management of runaway conditions such as: - - - Corrupted program counter Unexpected reset Critical Data corruption (control registers...)
Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the Reset pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
Table 17.
Symbol VFESD
EMS characteristics
Parameter Voltage limits to be applied on any I/O pin to induce a functional disturbance Fast transient voltage burst limits to be applied through 100 pF on VDD and VDD pins to induce a functional disturbance Conditions VDD=5 V, TA=+25 C, fOSC=8 MHz conforms to IEC 1000-4-2 VDD=5 V, TA=+25 C, fOSC=8 MHz conforms to IEC 1000-4-4 Level/ Class 2B
VFFTB
4B
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ST7LCR
4.7.2
Electromagnetic interference (EMI)
Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/3 which specifies the board and the loading of each pin. Table 18.
Symbol
EMI characteristics
Parameter Conditions Monitored Frequency Band 0.1 MHz to 30 MHz VDD=5 V, TA=+25 C, conforming to SAE J 1752/3 30 MHz to 130 MHz 130 MHz to 1 GHz SAE EMI Level Max vs. [fOSC/fCPU](1) 4/8MHz 4/4MHz 19 32 31 4 18 27 26 3.5 dBV Unit
SEMI
Peak level
1. Data based on characterization results, not tested in production.
4.7.3
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). The Human Body Model is simulated. This test conforms to the JESD22-A114A standard. Table 19.
Symbol VESD(HBM)
Absolute maximum ratings
Ratings Electrostatic discharge voltage (Human body model) Conditions TA=+25 C Maximum value(1) 2000 Unit V
1. Data based on characterization results, not tested in production.
Static and dynamic latch-up
LU: 3 complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181. DLU: Electrostatic discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. Power supplies are set to the typical values, the oscillator is connected
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ST7LCR as near as possible to the pins of the micro and the component is put in reset mode. This test conforms to the IEC1000-4-2 and SAEJ1752/3 standards. For more details, refer to the application note AN1181. Table 20.
Symbol LU DLU
Electrical sensitivities
Parameter Static latch-up class Dynamic latch-up class Conditions TA=+25C VDD=5.5V, fOSC=4MHz,TA=+25C Class(1) A A
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard).
4.8
Communication interface characteristics
Table 21. USB DC electrical characteristics
Symbol Conditions Min. Max. Unit Parameter Input levels Differential input sensitivity Differential common mode range Single ended receiver threshold Output levels Static output low Static output high USBVCC: voltage level VOL VOH USBV RL of 1.5 k to 3.6 V(1) RL of 15 k to VSS(1) VDD=5 V 2.8 3.00 0.3 3.6 3.60 V V V VDI VCM VSE I(D+, D-) Includes VDI range 0.2 0.8 1.3 2.5 2.0 V V V
1. RL is the load connected on the USB drivers. All the voltages are measured from the local ground potential.
Figure 6.
USB data signal rise and fall time
Differential
Data Lines VCRS
Crossover
points
VSS tf tr
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ST7LCR Table 22. USB full-speed electrical characteristics
Symbol Conditions Min Max Unit
Parameter Driver characteristics Rise time(1) Fall Time
(1)
tr tf trfm VCRS
CL=50 pF CL=50 pF tr/tf
4 4 90 1.3
20 20 110 2.0
ns ns % V
Rise/ Fall time matching Output signal crossover voltage
1. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to Chapter 7 (Electrical) of the USB specification (version 1.1).
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ST7LCR
5
Package characteristics
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) package. The package has a lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
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ST7LCR
5.1
Figure 7.
Package mechanical data
24-lead very thin fine pitch quad flat no-lead 5x5 mm 0.65 mm pitch, package outline
D e 19 K 18 E2 b 1 e E 24 A3
ddd
13 K2
6 12 D2 7 K2
L2 L A1 A
Y1_ME
Table 23.
Dim.
24-lead very thin fine pitch quad flat no-lead 5x5mm,0.65mm pitch, mechanical data
mm Min Typ 0.900 0.020 0.020 0.250 0.300 5.000 3.500 3.600 5.000 3.500 3.600 0.650 0.350 0.870 0.450 0.875 0.080 0.550 0.880 0.0138 0.0343 3.700 0.1378 3.700 0.1378 0.350 0.0098 Max 1.000 0.050 Min 0.0315 0.0000 inches(1) Typ 0.0354 0.0010 0.0008 0.0118 0.1969 0.1417 0.1969 0.1417 0.0256 0.0177 0.0344 0.0031 0.0217 0.0346 0.1457 0.1457 0.0138 Max 0.0394 0.0020
A A1 A3 b D D2 E D2 e L L2 ddd
0.800 0.000
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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ST7LCR Figure 8. Recommended reflow oven profile (MID JEDEC)
250 200 Temp. [C] 150 100 50 0 100 200 300 400
ramp up 2C/sec for 50sec 150 sec above 183C 90 sec at 125C Tmax=220+/-5C for 25 sec
ramp down natural 2C/sec max
Time [s]
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ST7LCR
6
Device configuration and ordering information
Device ordering information and transfer of customer code
Customer code is made up of the ROM contents and the list of the selected options (if any). The ROM contents are to be sent on diskette, or by electronic means, with the hexadecimal file in .S19 format generated by the development tool. All unused bytes must be set to FFh. The selected options are communicated to STMicroelectronics using the correctly completed OPTION LIST appended. See Figure 9: ST7LCR option list. Refer to application note AN1635 for information on the counter listing returned by ST after code has been transferred. The STMicroelectronics Sales Organization will be pleased to provide detailed information on contractual points. Table 24. Ordering information
Sales type ST7LCRE4U1/xxx(1) ST7LCRDIE6/xxx
(1)
Program memory (bytes) 16K ROM 16K ROM
RAM (bytes) 768 768
Package VFQFPN24 Die
1. Customer ROM code name is assigned by STMicroelectronics.
26/29
ST7LCR Figure 9. ST7LCR option list
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&XVWRPHU $GGUHVV &RQWDFW 3KRQH 1R

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27/29
ST7LCR
7
Revision history
Table 25.
Date 26-Aug-06
Document revision history
Revision 0.1 Initial release QFN24 package added Option List added External clock source frequency modified (to maximum value), Section 4.2 Die sales type added to Table Note added to Table 2 (NC pins must be connected to ground) Document reformatted. Replaced ST7LCR by ST7LCRE4U1and ST7LCRDIE6. ECOPACK text added. Changed "selectable card VCC" into "fixed card VCC". 5 V removed in Section : Features, Section 3: ST7LCR implementation and Table 16: Smartcard supply supervisor electrical characteristics. Changed QFN24 into VFQFPN24. Added Figure 8: Recommended reflow oven profile (MID JEDEC). CRDC4 and CRDC8 renamed C4 and C8 respectively in Figure 1: ST7LCR block diagram. Removed LED functional block and LEDO pin from Figure 1: ST7LCR block diagram. LEDO pin left unconnected in Figure 2: 24lead VFQFPN package pinout and Table 2: Pin description, and Figure 3: Smartcard interface reference application - VFQFPN24 pin block diagram. Removed mention of external LEDS in Section 3.1: Functionality. SLEF and DIODE pins removed from Figure 1: ST7LCR block diagram, and left unconnected in Figure 2: 24-lead VFQFPN package pinout,Table 2: Pin description, and Figure 3: Smartcard interface reference application - VFQFPN24 pin block diagram. Removed LED pin characteristics table. Added Figure 8: Recommended reflow oven profile (MID JEDEC). Updated Figure 9: ST7LCR option list. Changes
26-Mar-07
0.2
23-Oct-2007
1
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ST7LCR
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